library ieee;
use    ieee.std_logic_1164.all;
use    ieee.std_logic_unsigned.all;

entity  fiftymhz is
	port (  
          inp:  in std_logic;
          outp:  out std_logic
         );
end fiftymhz;

architecture a of fiftymhz is 
begin
    
    outp <= inp;
end a;
        